1. Technical Field
The present invention relates to a light weight and high throughput test case methodology. More particularly, the present invention relates to swapping test cases between homogeneous processors in order to effectively test the processors utilizing a reduced set of test cases.
2. Description of the Related Art
Processor testing tools exist whose goal is to generate the most stressful test case for a processor. In theory, the generated test case should provide maximum test coverage and should be interesting enough to stress various timing scenarios on the processor. The whole technology of these tools sits in the logic of building these test cases.
Verifying and validating a processor using test cases typically includes three stages, which are 1) test pattern build stage, 2) test pattern execution stage, and 3) validation and verification stage. The invention described herein pertains to utilizing a reduced set of test cases during the test pattern execution stage.